1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to an embedded memory integrated on a single semiconductor chip together with a processing device such as a logic. More specifically, the present invention relates to a configuration for reducing current consumption without deteriorating data hold characteristic of a memory cell in a deep power down mode (low current consumption stand-by mode) of an embedded DRAM (dynamic random access memory).
2. Description of the Background Art
In the fields of image data processing and the like, in order to perform high-speed data processing, a system LSI (large scale integrated circuit) in which a logic circuit such as a processor and a memory circuit are integrated on a single semiconductor chip has widely been used. In the system LSI, as the logic circuit and the memory circuit are interconnected via on-chip interconnects, the following advantageous effects are obtained:
(1) a load of a signal interconnection line is lower than that of an on-board interconnection line and data or a signal can be transmitted at high speed;
(2) as the number of pin terminals is not restricted, a data bus width can be greater and a bandwidth for data transfer can be greater;
(3) as each component is integrated on the single semiconductor chip, a small and compact system can be implemented; and
(4) a macro prepared as library can be arranged for a component to be formed on the semiconductor chip and design efficiency can be improved.
For these reasons, the system LSI is widely and commonly used in various fields as an SOC (system on chip) and the like.
In addition, examples of the memory circuit used in the system LSI cover, in addition to the DRAM, an SRAM (static random access memory), a flash memory (non-volatile semiconductor memory device), and the like. Further, examples of the logic circuit cover a processor for control and data processing, an analog processing circuit such as an A/D (analog/digital) conversion circuit, and a logic circuit dedicated to logic processing.
In the DRAM of an example of the memory circuit, a memory cell includes a capacitor and stores data in accordance with an amount of electric charges stored in the capacitor. In order to prevent loss of electric charges stored in the memory cell capacitor due to a leakage current or the like, a so-called refresh operation is required. The configuration of the memory cell, however, is relatively simple, and a memory with a small occupation area and a large storage capacity can be implemented. Therefore, the DRAM will increasingly be indispensable as the embedded memory in the system LSI of which amount of information processing increases.
The configuration of the DRAM used for such embedded memory is disclosed, for example, in Non Patent Document 1 (N. Watanabe et al., “An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester,” IEICE Trans. Electron., Vol. E86-C, No. 4, April 2003, pp. 624-632).
According to Non Patent Document 1, a memory cell array, an array control driver, a power supply circuit, a data path (a data input and output portion), a clock generator, and an internal operation timing generator are each prepared as macro, and a main control circuit and a local control circuit can be synthesized with software in accordance with applications/specifications. In addition, Non Patent Document 1 discloses a configuration for performing refresh in a bank basis as refresh operation control, with a memory cell array being divided into a plurality of banks.
When such embedded DRAM is applied to applications such as portable equipment, low power consumption is required. In the DRAM, however, electric charges stored in the memory cell capacitor are lost due to various types of leakage currents such as a junction leakage current at a storage node (connection node between the memory cell capacitor and an access transistor), a channel leakage current of a memory cell transistor (access transistor), a gate leakage current of a capacitor insulating film, and the like. Accordingly, refresh should be repeated at predetermined intervals such that refresh of all rows in the memory cell array is completed once in a refresh time period (tREF) determined by the memory cell with the worst data hold characteristic (shortest data holding time period) in the memory cell array.
In the refresh operation, a word line arranged corresponding to a memory cell row is driven to a selected state and storage data in the memory cells are read on corresponding bit line pairs. Thereafter, the storage data in the memory cell read on the bit line pair is amplified by an associated sense amplifier and the amplified data is written back again into the original memory cell. Therefore, as signal lines are charged and discharged and circuitry in a portion related to row selection operates, consumption of AC (alternating current)-wise current increases. In addition, with the increase in the storage capacity and shrinking in feature size, consumption of DC (direct current)-wise current due to an off-leakage current of the transistor in an internal circuit of the embedded DRAM also increases. Therefore, such AC current and DC current flow in a stand-by mode in which data is simply held and external data access is not carried out, and current consumption for data hold is an innegligible amount.
A configuration for reducing such current consumption in a stand-by mode is disclosed, for example, in Patent Document 1 (Japanese Patent Laying-Open No. 2005-353244). In Patent Document 1, the access transistor is configured with a P-channel MOS transistor (insulated gate type field effect transistor). In order to suppress loss of electric charges stored in the memory cell capacitor due to the off-leakage current of the access transistor, a word line voltage is varied between a high voltage VPP higher than a cell power supply voltage and a negative voltage VBB. When a word line is in a non-selected state (including a stand-by state), a word line voltage is at a high voltage VPP level, and when a word line is in a selected state, the word line voltage is set to negative voltage VBB.
Patent Document 1 considers such a problem in the word line drive scheme described above that, when a word line is selected, electric charges for charging the word line flow to a negative power supply node and negative voltage VBB becomes unstable, and accordingly current consumption in a negative voltage generation circuit becomes large. Specifically, in Patent Document 1, when a word line is selected, the word line is first coupled to a ground node and a voltage of the selected word line is transitioned to a ground voltage level. Thereafter, the selected word line is driven to the negative voltage level. The current that flows into the negative voltage generation circuit upon selection of the word line is reduced to a current comparable to a current flowing between the ground voltage and the negative voltage, thereby reducing noise on the negative voltage upon selection of the word line. In addition, current consumption in the negative voltage generation circuit is thus reduced.
Normally, the DRAM supports a power down mode in order to reduce power consumption in the stand-by mode. In the power down mode, supply of a power supply voltage to a circuit not related to the refresh operation (such as a column selection circuit and an input and output circuit) is stopped. In this case, however, power is constantly supplied to circuitry related to the refresh operation (a word line selection circuit and a sense amplifier circuit).
A configuration for further reducing current consumption in such power down mode is disclosed, for example, in Patent Document 2 (Japanese Patent Laying-Open No. 2000-173263). In the configuration disclosed in Patent Document 2, a word line is formed into a hierarchical word line structure including main and sub word lines. The access transistor in the memory cell is formed of an N-channel transistor. During non-selected state or stand-by, a main word line is maintained at H level (logical high level) and a sub word line is maintained at L level (logical low level). High voltage VPP and a ground voltage VSS are supplied to a word line driver as an operating power supply voltage. The word line driver is configured with inverters of two stages. A latch transistor latching an input portion voltage in accordance with an output voltage of an inverter in the first stage is provided at the input portion of the inverter in the first stage. A high-side power supply line (high voltage line) and a low-side power supply line (ground line) of these inverters of two stages are arranged in a hierarchical structure. During the stand-by cycle, in accordance with output voltage levels of these inverters, power supply to one of these operating power supply voltages is stopped. Specifically, as the inverter at the first stage outputs a signal at L level during stand-by, supply of the high-side power supply voltage is stopped. As a drive inverter in the next stage outputs H level (high voltage level) during stand-by, supply of the low-side power supply voltage is stopped. Thus, in a stand-by cycle, leakage current that flows from the high voltage node to the ground node through a transistor in an OFF state is suppressed.
In a portable terminal such as a portable phone, as a battery is used as the power supply, current consumption is required to be reduced as possible extent. In order to further reduce current consumption in the stand-by mode, a deep power down mode is employed. In the deep power down mode, supply of the power supply voltage and the internal voltage to the embedded DRAM is stopped. In performing refresh, necessary power supply voltage and internal voltage are supplied so as to perform refresh. Therefore, supply of the power supply voltage and the internal voltage is stopped in the stand-by cycle and no leakage current flowing path exists.
As disclosed in aforementioned Patent Document 1, however, when a P-channel MOS transistor is used as the memory cell transistor, the word line voltage should be maintained at the high voltage level during the stand-by state in the deep power down mode. This is because, when the word line voltage is lowered, the access transistor is rendered conductive, electric charges stored in the capacitor flow away, and data stored in the memory cell is lost.
Non Patent Document 1 described previously merely discloses a macro configuration of a general embedded DRAM and does not consider current consumption in the stand-by mode nor an operation in the power down mode or the deep power down mode.
Patent Document 1 merely considers instability of a word line selection voltage (negative voltage) in selecting a word line and current consumption in a selection voltage (negative voltage) generation portion. Patent Document 1 does not consider a configuration for reducing current consumption in the stand-by mode such as the power down mode or the deep power down mode.
According to Patent Document 2, the leakage current path in the word line driver is cut off in the power down mode. In the power down mode, however, the high voltage is constantly supplied to the word line driver that serves as the circuit related to refresh. Patent Document 2 does not consider a configuration for cutting off supply of the power supply voltage and the internal voltage even to the circuit related to refresh, as in the deep power down mode. In addition, the word line driver is merely supplied with the high voltage and the ground voltage. Patent Document 2 does not consider a configuration for suppressing lowering in the high voltage in the stand-by mode, in a driver configuration in which three kinds of voltages of high voltage, ground voltage and negative voltage are supplied.
In addition, in the configuration according to Patent Document 2, the memory cell transistor is configured with the N-channel transistor. Normally, a sub word line driver provided for a sub word line drives the sub word line in accordance with a voltage of a corresponding main word line. The sub word line driver receives a sub decode signal at an operating power supply node. The sub decode signal is set to L level in the stand-by state. Therefore, even when the voltage of the main word line lowers due to the leakage current and a gate potential in the transistor of the sub word line driver lowers during the stand-by cycle, the potential of the sub word line is not raised. In the configuration according to Patent Document 2, even if the voltage of the main word line lowers during the stand-by cycle, the access transistor in the memory cell is set to a shallow ON state and it is less likely that data stored in the memory cell is lost. Patent Document 2 does not consider the data hold characteristic of the memory cell in the deep power down mode in which supply of the power supply voltage and the internal voltage is stopped.